Note: The job is a remote job and is open to candidates in USA. Quest Global is seeking a Physical Design Engineer to work on the end-to-end physical implementation of complex SoCs. The role involves responsibilities such as full-chip or block-level physical design, timing closure, and collaboration with various teams to ensure design feasibility and performance goals.

Responsibilities

• Own full-chip or block-level physical design from synthesis to GDSII
• Perform floorplanning, placement, clock tree synthesis (CTS), routing, and optimization
• Drive timing closure, power optimization, and signal integrity improvements
• Analyze and resolve DRC/LVS, IR drop, EM, and noise issues
• Collaborate with RTL, architecture, and verification teams to ensure design feasibility and performance goals
• Work with foundries and EDA vendors to adopt best practices and methodologies
• Develop and improve automation scripts and flows for design efficiency
• Participate in design reviews and tapeout activities

Skills

• Bachelor's or Master's degree in Electrical Engineering, Electronics, or related field
• 5–10+ years of experience in physical design / VLSI backend
• Place & Route tools (Cadence Innovus, Synopsys ICC2/Fusion Compiler)
• Static Timing Analysis (STA) (PrimeTime, Tempus)
• Synthesis tools (Design Compiler, Genus)
• Solid understanding of physical design concepts: floorplanning, CTS, routing
• Low-power design techniques
• Timing closure methodologies
• Scripting skills in TCL, Python, or Perl
• Experience with advanced nodes (7nm, 5nm, 3nm)
• Knowledge of high-performance CPU/GPU/AI accelerator designs
• Familiarity with signal integrity, IR drop, EM analysis
• DFT/scan insertion awareness
• Experience in chip tapeout cycles
• Exposure to SoC-level integration
• Strong debugging and problem-solving skills

Company Overview

Company H1B Sponsorship