Note: The job is a remote job and is open to candidates in USA. Dice is seeking a Power Engineer specializing in ASIC SoC design. The role involves performing power analysis, optimizing design flows, and collaborating with the physical design team to enhance power efficiency.

Responsibilities

• Perform comprehensive power analysis in vector and vector-less modes of ASIC SoC design at different design stages from RTL to gate-level netlist
• Contribute to develop, improve, and automate power analysis flows
• Investigate power inefficiencies and provide feedback to design teams
• Present the results in a weekly meeting to wider audience
• Work closely with physical design team for clock tree, floorplan and physical implementation optimization
• Participate in memory power optimization through memory selection and traffic optimization
• Perform Synthesis and Physical design trials for optimal PPA recipes

Skills

• Understanding of Synopsys power flows (PTPX + PRRTL)
• Some PD background or understanding of netlist, UPF, SPEF
• Scripting knowledge - Python (required) + tcl. Excel/Gsheet (nice to have)
• Power optimization experience or understanding design+uArch for NoC+Clocking
• Some background on CTS
• Understanding of power fundamentals and experience with Synopsys power estimation tools (PrimePower, PPRTL)
• Familiarity with Syn-PnR flows using Synopsys Fusion Compiler (and RTL-A)
• Ability to develop and maintain automation scripts (preferably in Python) to streamline design flows and improve process efficiency
• 3-6 years of experience in Primepower or PowerArtist or Voltus - Mandatory
• Working knowledge of Tcl - Mandatory
• Python knowledge - Good to have
• RTL2GDSII design flow usage & development in advanced technology nodes (7nm and below)
• Low power implementation and signoff, power gating, multiple voltage rails, UPF/CPF usage
• Experience in power analysis and reduction using PrimeTime PX/PrimePower
• Proficiency in scripting languages such as Python and/or Perl is required
• Proficiency with TCL is required
• Familiarity with low power implementation techniques, clock gating, power gating etc
• Good written and verbal communication skills
• Familiarity with memories (SRAM/DRAM/RF/Flop based fifos)
• Experience with synth, PnR flows
• Power and performance implications with latest technology nodes
• Proficiency with version control systems
• Experience with rtl power optimization using tools such as Power-Artist
• Experience with library characterization tools and analysis
• Experience with FSDB analysis for design profiling

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