Senior DFT Engineer – Qualitest Location: Remote, UK. Start: ASAP We’re looking for multiple experienced DFT Engineers to join a cutting-edge programme with one of the world’s largest and most innovative technology companies, working remotely in the UK. This role focuses on developing and executing DFT strategies including scan design, ATPG, and verification, collaborating with world-class engineering teams to deliver high-quality silicon solutions in a fast-paced ASIC/SoC environment. Job responsibilities Develop DFT strategy for hierarchical DFT, Scan, and Automatic Test Pattern Generation (ATPG). Perform ATPG, scan coverage debug and drive design fixes for coverage and quality improvements Perform scan verification at RTL and gate level Prepare scan content and deliverables for Silicon Engineering execution Debug scan patterns on tester per requirement Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT Scan requirements are met and mutual dependencies are managed. Minimum qualifications Bachelor’s degree in electrical engineering, Computer Engineering, or a related field, or equivalent practical experience. Experience with multiple projects in DFT scan design and verification. Experience with DFT techniques and tools, ASIC DFT synthesis, simulation, and verification flow. Experience in Automatic Test Pattern Generation (ATPG) methods. Preferred qualifications Familiar with EDA tools like mentor (Tessent) from Siemens. Master’s degree in electrical engineering. Experience in IP integration (e.g., memories, test controllers, Test Access Point (TAP), and Memory Built-In Self-Test (MBIST). Experience in fault modelling. Experience in SoC cycles, including silicon bring up and silicon debug activities. Experience working with ATE engineers (e.g., silicon bring-up, patterns generation, debug, validation on automatic test equipment, debug of silicon issues).